1. Field of the Invention
The present invention relates to a method of manufacturing a nonvolatile semiconductor storage device having a floating gate, such as a flash memory.
2. Description of the Related Art
Patent Document 1: JP-A-62-131582
Patent Document 2: JP-A-5-175508
Patent Document 3: JP-A-6-188431
FIGS. 2A to C are constructional views of a storage element in a prior-art nonvolatile semiconductor storage device.
The storage element is formed in such a way that the front surface of a semiconductor substrate 1 is divided by an element isolation region 2, and that, on each active region of the semiconductor substrate 1 divided by the element isolation region 2, the layers of a floating gate 4, an inter-gate insulating film 5 and a control gate 6 are successively stacked through a tunnel oxide film 3 being about 10 nm thick and are thereafter patterned. Besides, diffused layers 7, 8 to become a source electrode and a drain electrode are respectively formed in the parts of the active region corresponding to both the sides of the storage element. The storage element is electrically programmed or erased in such a way that a voltage is applied between the control gate 6 and the diffused layers 7, 8 or semiconductor substrate 1, whereby charges are accumulated into the floating gate 4 located therebetween, or charges accumulated in the floating gate 4 are discharged.
In the prior-art storage element, the inter-gate insulating film 5 between the floating gate 4 and the control gate 6 is formed under predetermined conditions, so that the parts of the inter-gate insulating film 5 formed on the front surface and side surfaces of the floating gate 4 come to have substantially equal thicknesses. Accordingly, the part of the inter-gate insulating film 5 corresponding to the edge part of the front surface of the floating gate 4 becomes thinner than the other part, and the potential gradient of the edge part enlarges, to incur the problem that erroneous programming or erroneous erasing occurs or that the retention of the charges is adversely affected.